1. Field of the Invention
The present invention relates to a highly integrated semiconductor device having a multi-layer wiring structure, and more particularly, a process for fabricating a metal plug adapted to electrically connect metal wiring layers formed above and beneath an interlayer insulating film in such a semiconductor device.
2. Description of the Prior Art
Generally, such a metal plug is fabricated by forming a contact hole in an interlayer insulating film, forming a silicide film on the bottom surface of the silicide film, and forming a metal layer over the silicide film to fill the contact hole. However, this conventional method has a problem that the silicide film is incompletely formed so that a lower conduction layer is exposed to the metal plug at the peripheral edge of the contact hole. An incomplete silicide film thereby results in an occurrence of a junction consumption reaction and the fabrication of a metal plug having an irregular surface. Such problems encountered in the conventional method will be apparent by referring to the following descriptions made in conjunction with FIGS. 1A and 1B.
FIG. 1A illustrates a semiconductor device having a structure which includes a silicon substrate 10, an insulating film 12 disposed on the silicon substrate 10 and a contact hole 13 formed in the insulating film 12 such that the silicon substrate 10 is partially exposed. On the bottom surface of the contact hole 13, a metallic silicide film 14 is formed such that the silicon substrate 10 is partially exposed at the peripheral edge of the contact hole 13. The formation of the metallic silicide film is achieved by depositing a metal layer made of, for example, titanium, over the bottom surface of the contact hole 13 by use of physical vapor deposition (PVD) process and then annealing the metal layer. The metal layer has a weak portion disposed at the peripheral edge of the contact hole 13. This weak portion of the metal layer is removed by dry treatment. Due to the removal of the weak portion of the metal layer, the silicon substrate 10 is partially exposed at the peripheral edge of the contact hole 13, as mentioned above.
Referring to FIG. 1B, a metal plug 16 is formed in the contact hole 13 to have a recess 15 at the central portion thereof. The formation of the metal plug 16 is achieved by depositing a metal layer made of, for example, tungsten, over the bottom surface of the contact hole 13. The metal plug 16 is in contact with the silicon substrate 10 exposed at the peripheral edge of the contact hole 13. As a result, a junction consumption reaction occurs. The reason why the recess 15 is formed at the upper portion of the metal plug 16 is that the metal from the metal layer forming the metal plug 16 grows on the peripheral edge of the contact hole 13 at a higher rate than that on the central portion of the contact hole 13 due to different incubation times of the metal growing on the silicon substrate 10 and the metallic silicide film 14, thereby causing the metal to be deposited beyond the contact hole 13 and even on the surface of the insulating film 12. Due to the recess 15 formed at the upper surface of the metal plug 16, it is impossible to obtain a uniform coverage of a wiring layer (not shown) formed over the metal plug 16.